NICTA Embedded Systems Public Seminar
Compiling for EDGE Architectures: The TRIPS Prototype Compiler
Kathryn McKinley, University of Texas.
Time/Venue
Friday 08 February 2008, 2 pm
National ICT Australia Ltd, Level 1 Seminar Room, 223 Anzac Parade (Building L5), Kensington NSW 2052
Abstract
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE (Explicit Dataflow Graph Execution) architectures are one example of communication-exposed microarchitectures in which the compiler forms blocks that execute atomically. Each block consists of dataflow instructions where the compiler specifies their location on the architecture. In this talk, we present the TRIPS prototype EDGE architecture and the new balance it strikes between software and hardware responsibilities. We overview how the compiler generates correct code; new algorithms for creating high performance blocks full of useful instructions; and spatial path scheduling, a new algorithm that reasons explicitly about instruction parallelism, communication latencies, and path anchor points (fixed locations such as registers in the architecture).
We present results from our working TRIPS chip, designed and built by our group. Although we have not yet solved all the compilation challenges EDGE architectures pose, our results indicate there is potential for EDGE architectures to achieve power-efficient high performance while scaling with technology.
Biography
Kathryn McKinley is a professor at the University of Texas. Her research interests include compiler optimization, architecture, memory management, and software engineering. She is currently serving as the Editor-and-Chief of TOPLAS and has been the program chair of ASPLOS, PACT and PLDI. She has graduated eight PhD students and is currently supervising eight graduate students.